1. Field of the Invention
The invention relates to a memory having fast reading time. More particularly, the invention relates to non-volatile memories comprising floating gate transistors, having a reading time smaller than 100 nanoseconds.
2. Discussion of the Related Art
Nonvolatile memories having floating-gate transistors are of the so-called EPROM or EEPROM or even FLASH-EPROM type depending on the mode of programming and the mode of erasure chosen for the memory cells. An example of this type of memory is described for example in the patent application FR-A-2 714 202. The usual elementary reading time of a bit or word in a memory of this kind is about 100 nanoseconds.
The principle of the reading of the memory cells comprising a floating-gate transistor is as follows. In the floating gate of the transistor, charges are either stored or not, depending on whether the transistor is said to be programmed or erased (or vice versa, as the designations used differ from one technology to another). In one example, the charges stored are electrons. The floating gate then acts as a potential generator. When a cell is to be read, the drain and source regions of this transistor are subjected to a sufficient potential difference and a voltage capable of making the control gate of the floating-gate transistor conductive is applied to it. If there are no electrical charges stored on the floating-gate, the transistor becomes conductive. If there are electrical charges stored on the floating gate, the voltage applied to the control gate is insufficient to combat the potential induced by the floating gate and thus the transistor does not conduct. A read circuit, in principle, has a device that measures the presence or absence of conduction current through the transistor. The detection or non-detection of this passage of current provides information on the binary state memorized in the memory cell.
FIG. 1 provides a schematic view of a memory cell of this kind with a floating-gate transistor. This transistor has a source 1 connected to a ground and a drain 2 connected to a bit line LB 3. Bit line 3 is connected to a current measurement circuit (not shown) which, in practice, is a voltage generator with high internal impedance. As soon as the generator lets through current, the voltage on bit line 3 drops. The transistor of the memory cell furthermore has a floating gate 4 and a control gate 5 superimposed on the floating gate 4 and playing the role of a word line LM. The memory array of a memory has several cells of this type connected in matrix form to the bit lines and to the word lines.
As a general rule, the bit line is formed, at the top of the integrated circuit, by a metallized line: it has very low resistivity. Consequently, the propagation of the read voltage on a bit line is very swift. By contrast, the word line 5 consists of a polysilicon layer: it is resistive. Even if the word line has metallized sections, the word line still consists of polysilicon sections such that word line 5 remains more resistant than the bit line 3. In view of the surfaces presented by these conduction lines with respect to the memory array, these lines are capacitive. Since the word line is more resistive than the bit line, it is slower in allowing the necessary read voltage to build up.
At the time of reading, the build-up of the different potentials on the lines must be synchronized allowing the word line sufficient time to build up voltage on the gate. For example, at the detection of an address transition signal, when a new word or a new cell of the memory is addressed to be read, there is no point in immediately preparing the read circuit connected to the bit line (this is a preparation that lasts about 10 nanoseconds) if in the meantime the word line takes about 80 nanoseconds to get charged.
FIG. 2 furthermore shows the behavior of a floating-gate transistor of a memory cell whose word line receives a potential VLM that increases slowly (taking every factor into consideration) starting from an instant t0 corresponding to a detection of an address transition. In one example where the conduction threshold VT of a floating-gate transistor is about 2 to 3 volts and where the electrical supply of the integrated circuit is about 5 volts, a value of 4 volts (80% of the electrical supply) is chosen as being the value necessarily applied to the control gate 4 to make the transistor conductive. For example, FIG. 2 shows that when the applied voltage is equal to VT, the conduction current I of the transistor begins to increase. It reaches a significant value which allows reading of the transistor only when the voltage on the word line is equal to approximately 4 volts (80% of the electrical supply). It is important to have precise knowledge of the time t at which, for a given integrated circuit, this reading will be possible.
Unfortunately, the time t greatly depends on the design of the different transistors, the chronology of the steps of the method leading to the manufacture of the integrated circuit, as well as the conditions of use of this circuit, especially the value of the supply voltage and the temperature of use. For example, it is known that the value of t varies greatly, for example between 50 nanoseconds for a naturally fast circuit and 100 nanoseconds for a slow circuit. The reasons for the speed variations can be understood from FIG. 2. When the cell becomes conductive, the current I increases suddenly and the slope of growth of the voltage on the word line is small. Consequently, a very small disturbance in the polarization of these word lines or in the operating conditions of the floating-gate transistors is sufficient to result in great variations in the activation instant t, i.e., the time VT is reached indicated in the figure by means of dashes.
In the prior art, to overcome this problem, and to obtain the value of t, the voltage build-up time of the word lines is simulated on an additional word line or false word line. In practice, the false word line has been simulated by a single RC type circuit. However, in order to have time constants that are independent of temperature and supply voltage and of the method of manufacture of the integrated circuit, it has become necessary to make BANDGAP type circuits or circuits with bipolar transistors. Apart from their complexity, these circuits have the drawback of consuming current continuously if speed is to be obtained. All the same, it is necessary to take account of worse-case situations with these circuits, namely cases where the period is 100 nanoseconds.
Another problem also arises. Indeed, it is possible that the address bus connected to the memory will be badly managed and deliver false addresses in an anarchic manner even for a certain period. These false addresses are detected by the address transition detection circuit and normally prompt a build-up in voltage of the false word line which will be used to prepare the activation time t, the instant of synchronization of the reading. When the detection is a parasitic address transition detection, it is necessary, at a subsequent address transition detection, to swiftly discharge the false word line from the voltage to which it has risen and then begin charging it again towards its nominal voltage.
There are approaches in which the false word line of the RC type is provided with several capacitors distributed along the line and, to discharge it, with several big deselection transistors parallel-connected with these transistors. They make it possible to reposition the false word line at zero before making the voltage rise again. In one example, there are known word lines with 1000 cells in which it is necessary to have eight big transistors separating groups of 128 cells. However, the distribution of these eight big transistors modifies the rules of design: the pattern of the cells is no longer repetitive (it has to be modified every 128 cells) and the making of the integrated circuit becomes far too complex.
In practice, this is not done. To simplify matters, a simple RC type circuit is made with a single deselection transistor. The problem encountered in this case is that the RC type circuit has characteristics that change greatly with temperature and supply voltage. It is therefore necessary then once again to choose a worst-case situation for this RC type circuit. Ultimately, the memory is made to work in a slowed down manner.